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Additional info for Automatic Layout Modification: Including Design Reuse of the Alpha CPU in 0.13 Micron SOI Technology
This Figure shows the PSM of a gate and how the image looks on the wafer. This is a technique for producing transistor gates with smaller gate lengths, even when the poly width has to be a larger size. Creating a PSM mask for an entire poly or metal layer is very difficult because of phase shift conflicts. 50 Chapter 3 In Figure 3-32 a T-shaped polygon is drawn. On one side of the T is a 0phase PSM polygon, and on the other side is a 1-phase polygon. The question now is which mask to put at the top of the T.
This means that clock signals have to be shielded from, or spaced more widely to, other signals. A better and more accurate solution would be to take the detailed capacitance and resistance of every branch of the clock tree into account. By making a detailed analysis and specifically changing the width and spacing of each branch of the clock tree, a better clock skew optimization is possible. 5 Solving Signal Integrity Problems In DSM Circuits In DSM circuits, signal integrity effects can lead to circuit malfunction.
Other approaches also reduce the sizes of transistors that are part of the load of the critical delay path. This reduces the load of the driving transistors, and speeds up the signal. The combination of enlarging and reducing transistor sizes also improves power consumption. Boosting Design Capabilities with ALM Technology 39 Often the layout topology does not allow simply increasing the width of the transistor. In many cases, fingers must be added or deleted to implement the correct gate size.